Serve as the AMD technical owner of various 3 rd party SERDES and other mixed signal IP. Provide pre and post silicon IP leadership and support for SerDes PHYs and other mixed signal IP, in particular IP like PCIe, Ethernet, UCIe, USB, MIPI, and Display PHYs, plus PLLs and miscellaneous IOs and circuits. Work directly with 3 rd party IP vendors to support design transfer,